Mastering Technologies for Scalable Spin-based Solid-State Quantum Processors
Currently world-wide efforts are concentrated along research and industrial developments of quantum computers based on large cryogenic or vacuum installations, having attracted massive investments. Nevertheless, an integrable portable quantum processor, operating at ambient conditions, would bring massive benefits for developing quantum algorithms, software and novel applications, widely spreading the quantum technologies. The research on the realisation of integrable devices is also subject to several research activities within the Quantum Flagship. However, these concepts represent chief technical challenges in terms of scalability of qubit gates that are still limited to operation of only a very few qubits and requiring temperatures of a few milliKelvin. An integrable, small to medium scale and portable quantum processor, operating at ambient conditions, represents thus chief technical challenges in terms of development of concepts and technologies. Photonic technologies represent the major development trends towards integrable devices, offering the potential of operating a large number of qubits, still the current photonic technologies are probabilistic.
The recent breakthrough results, established within this consortium, discovered the possibility of near-deterministic generation of solid-state-qubits, NV centres in diamond, placed at a distance of about 10-40 nm allowing for high-fidelity two-qubit gates based on magnetic dipole-dipole coupling. The method of electrical readout of the spin, also discovered last year by the consortium members, allows for individual spin qubit readout, dealing with the major constrain of the diamond quantum hardware scalability. MAESTRO proposes a novel approach to develop solid-state qubit architectures for working at ambient conditions, which become available based on the aforementioned ground-breaking work, that will be used as a basis for scaling up, providing a compelling path towards industrially interesting medium scale quantum systems. The central aim of the proposal is to tackle the bottle neck issues of our technology for diamond processor hardware scalability, e.g., the deterministic engineering and fabrication of NV qubits with a high fabrication yield that will allow then to scale our technology to industrially relevant processes. Together with the selective electric qubit readout, applied to an entangled qubit network in a nanoscale device, MAESTRO will provide a quantum processor platform that can be further developed, in future, towards marketable industrial applications.
- Coordinator: Milos Nesladek (Hasselt University, BE)
- Mario Baehr (CiS Forschungs-institut für Mikrosensorik GmbH, DE)
- Alexandre Tallaire (Institut de Recherche de Chimie Paris, FR)
- Jocelyn Achard (Laboratoire des Sciences des Procédés et des Matériaux, FR)
- Marius Grundmann (SaxonQ GmbH, DE)
- Jan Meijer (Leipzig University, DE)
- Fedor Jelezko (Ulm University, DE)
- Adam Gali (Wigner Research Centre for Physics, HU)