Scalable Architecture for Ion-Trap Quantum Computing Integration

The realization of the European quantum computing roadmap requires new quantum computing architectures that enable a scalable approach towards the goal of a thousand qubits at the end of the decade – a challenge that ought to be tackled in a collaborative effort across disciplines such as quantum science, computer science, and electrical engineering. In this project we propose to develop intermediate-scale quantum computation devices and complement the hardware with device-aware compilers for the trapped-ion platform. The project cross-fertilizes three critical areas:

– ion-trap development, pushing towards segmented ion traps with low heating rates;

– efficient compilation of quantum algorithms into low-level instruction circuits for segmented quantum information processing that enable seamless integration of qubit shuttling operations;

– scalable, low noise electronic circuits development for fast operation of segmented ion-trap quantum information processors at room temperature and cryogenic conditions.

During the project we will integrate the developed electronics, compilers and ion traps in a prototype and deploy it for use in R&D, academic and industrial applications. Developed with the long-term vision of pushing towards 1000 qubits in mind, the realized technology will serve as a platform to drive the European quantum computation roadmap.

CONSORTIUM

• Coordinator: Thomas Monz (Alpine Quantum Techlogies GmbH, AT)
  
• Henrik Dreyer (Cambridge Quantum Deutschland GmbH i.G., DE)
• Grzegorz Kasprowicz (Institute of Electronic Systems,Warsaw University of Technology, PL)

PROJECT POSTER: SIQCI